module rtl8201_initialize
(
    input       wire        sys_clk,
    input       wire        sys_rst,






    output      wire        ready,
    output      wire        phyrst,
    output      wire        mdc,
    inout       wire        mdio

);
//logic [31:0] ip_adr = {8'd192,8'd168,8'd15,8'd16};






reg             rphyrst;
reg             phy_rdy;
reg             SMI_trg;
reg             SMI_rw;
reg     [4:0]   SMI_adr;
reg     [15:0]  SMI_wdata;
reg     [7:0]   SMI_status;




wire             SMI_ack;
wire             SMI_ready;
wire     [15:0]  SMI_data;

assign mdc = sys_clk;
assign ready = phy_rdy;
assign phyrst = rphyrst;


always@(posedge sys_clk or negedge sys_rst)begin
    if(sys_rst == 1'b0)begin
        phy_rdy <= 1'b0;
        rphyrst <= 1'b0;
        SMI_trg <= 1'b0;
        SMI_adr <= 5'd1;
        SMI_rw <= 1'b1;
        SMI_status <= 0;
    end else begin
        rphyrst <= 1'b1;
        if(phy_rdy == 1'b0)begin
            SMI_trg <= 1'b1;
            if(SMI_ack && SMI_ready)begin
                case(SMI_status)
                    0:begin
                        SMI_adr <= 5'd31;
                        SMI_wdata <= 16'h7;
                        SMI_rw <= 1'b0;

                        SMI_status <= 1;
                    end
                    1:begin
                        SMI_adr <= 5'd16;
                        SMI_wdata <= 16'hFFE;

                        SMI_status <= 2;
                    end
                    2:begin
                        SMI_rw <= 1'b1;

                        SMI_status <= 3;
                    end
                    3:begin
                        SMI_adr <= 5'd31;
                        SMI_wdata <= 16'h0;
                        SMI_rw <= 1'b0;

                        SMI_status <= 4;
                    end
                    4:begin
                        SMI_adr <= 5'd1;
                        SMI_rw <= 1'b1;

                        SMI_status <= 5;
                    end
                    5:begin
                        if(SMI_data[2])begin
                            phy_rdy <= 1'b1;
                            SMI_trg <= 1'b0;
                        end
                    end
                endcase
            end
        end
    end
end




mdio    mdio_inst0
(
    .clk        (sys_clk    ), 
    .rst        (rphyrst    ), 
    .rw         (SMI_rw     ), 
    .trg        (SMI_trg    ),
    
    
    .phy_adr    (5'd1       ), 
    .reg_adr    (SMI_adr    ),
    .data       (SMI_wdata  ),
    
    .ready      (SMI_ready  ), 
    .ack        (SMI_ack    ),
    
    .smi_data   (SMI_data   ),
    .mdio       (mdio       )
);

endmodule